1. Field of the Invention
The present invention relates to a microcomputer having a built-in serial input-output circuit.
2. Description of the Prior Art
FIG. 7 is a block diagram showing the internal configuration of a conventional one-chip microcomputer shown in the user""s manual (issued on October 1990 by Mitsubishi Electric Corporation) for a one-chip microcomputer M38063 M6-XXXFP/GP manufactured by Mitsubishi Electric Corporation. In the figure, 101 is a CPU which executes predetermined operation or control according to a program stored in a ROM 102, 103 is a RAM for storing data, 104 is a timer for measuring necessary period of time, etc., 105 is an input-output port (IO port) for exchanging data with an external circuit, 106 is a D-A converter which converts digital values into analog values and outputs them to the external circuit, 107 is an A-D converter which converts analog values into digital values and outputs them to the external circuit, 108 is a serial input-output circuit (SIO) which converts serial data from the external circuit into parallel data, and converts parallel data into serial data and outputs them to the external circuit, 109 is a clock signal generator, and 110 is a data bus. In the case of this microcomputer, an input-output line for the D-A converter 106, the A-D converter 107 and the SIO 108 is used in common with an input-output line for IO port 105.
FIG. 8 is a block diagram showing the internal configuration of the SIO 108 which is shown in the above-mentioned user""s manual. In the figure, 51a is a frequency divider which divides the frequency of a clock signal from an Xin to a xc2xc frequency, 51b is a frequency divider which further divides the above divided frequency to a xc2xc frequency, 52 is a switch for selecting a clock signal either a clock signal of the xc2xc frequency or a clock signal of the {fraction (1/16)} frequency, 53 is a counter for further dividing the frequency of the clock signal of the divided frequency, 54 is a switch for selecting a clock signal out of signals of divided frequencies which are obtained by further division of the frequency of the signal input to the counter 53, 55 is an SIO counter which counts the frequency of a clock signal from the switch 54, and 56 is an SIO register which converts the serial data input from an Sin terminal into parallel data according to a clock signal from the switch 54 and also converts parallel data into serial data according to the clock signal from the switch 54 and outputs them to an Sout terminal.
Next, the operation will be explained. In this place, the operation concerning the SIO 108 will be explained. In a case of transmission, the CPU 101 writes the transmission data to the SIO register 56 after the execution of a predetermined setting for the IO port 105. The SIO register 56 shifts data according to the clock signal from the switch 54. The bits squeezed out of SIO register 56 are output to the Sout terminal. When the SIO counter 55 is informed that all data are output to the Sout terminal by a count value, it gives an interrupt signal to the CPU 101. If there are data to be transmitted, CPU 101 writes the data to the SIO register 56.
In a receiving period, the SIO register 56 takes in data input from the Sin terminal according to the clock signal from the switch 54 and shifts them bit by bit. When the SIO counter 55 is informed that the quantity of data corresponding to the capacity of the SIO register 56 is input to it by a count value, it gives an interrupt signal to the CPU 101 for example. Then the CPU 101 takes in data from the SIO register 56.
In the above explanation, the clock signal from the switch 54, that is, the internal clock signal is used as a clock signal to shift the contents of the SIO register 56; however, a clock signal supplied from an external circuit can be also used.
It is considered to constitute a LAN utilizing the SIO function of a microcomputer. For example, there is an ISO/DIS 11519-3 (J1850) LAN standard as a standard which is applicable to such a LAN. The J1850 standard is of a bus type LAN standard, which is so called a multimaster system. In the J1850 standard, there is a period of time in which respective terminal stations output their address signals following to the period of time for outputting start bits. When a certain terminal station, a certain microcomputer in this place, send out a start bit to a bus, other microcomputers which desire to send out data start to output start bits to the bus simultaneously. Further, respective microcomputers send out their addresses in synchronization to the bus. The data such as start bits or addresses are PWM pulses. The respective addresses are so allotted that an address of a microcomputer of a highest priority is left on the bus.
The data on the bus are compared with the address of a terminal station and if they coincide a transmitting right is allotted to the terminal station. The process for acquiring the transmitting right is called arbitration, and the comparison between the data on the bus and the address of the terminal station is called arbitration judgment. It is shown in an example shown in FIG. 9 that since a third bit in an address sent out by a microcomputer on a A side does not coincide with the address on the bus, the microcomputer on the A side stops the transmission of data after the output of the address, and an address sent out by a microcomputer on a B side coincides with that on the bus, so that the microcomputer on the B side continues transmission of data.
In order to make such arbitration judgment possible, the timing of a start bit has to be strictly detected in a microcomputer. Otherwise, the sending-out timings of respective microcomputers are dispersed and judgment will be made impossible. If it is desired to realize the timing detection of a start bit in a conventional microcomputer, at first, the realization in using software is considered. In other words, the bus is introduced with one bit of the input port and the appearance of a start bit on the bus is detected by software. However, it requires more than several machine cycles to detect the existence of a start bit on the bus in searching the input port, so that the detection of the bit can be too late. The input port has to be supervised by the software all the time, and the occupying time of the CPU by the soft ware is lengthened. Therefore actually, it will be difficult to execute arbitration judgment by software.
It is also considered to realize the arbitration with hardware, wherein the output of data in the SIO register 56 is made enable by the start bit. However, the timing of the start bit and a clock signal to be given to the SIO register 56 are asynchronous. Therefore, there is probability of the occurrence of delay of 1 clock pulse cycle at a maximum from the timing of a start bit to the sending-out timing of data in the SIO register 56.
In the above explanation, a LAN according to the J1850 standard is taken up as an example; however, in the case of a conventional SIO, there is always the probability of delay in a start of sending out of transmitting data as far as a method is used in which the sending out of transmission data is stated by a trigger signal. As described in the above, in a case where data check on a bus in a LAN is performed, much time is needed for executing the program, so that the period of time to be shared for other processes, (a protocol control process, for example) is decreased. Therefore, if the transfer speed of a LAN is upgraded, there is a probability that the period of time to be shared for other software processes is made insufficient. In other words, in a case where data check on the bus in a LAN is performed by software, it is impossible to improve much the transfer speed of data in the LAN.
Since a conventional microcomputer is constituted as described in the above, there is a problem that a built-in SIO 108 cannot be utilized fully in the LAN which requires strict timing control for an arbitration judgment, etc. There is also another problem that a load on the software is heavy, so that the system is not able to correspond to a high speed serial communication.
The present invention is invented to solve the problems as described in the above, and an object of the present invention is to offer a microcomputer having a built-in SIO which is able to correspond to a LAN which requires strict timing control and also to correspond to a high speed serial communication.
A microcomputer according to the present invention comprises an initialization means for initializing a clock signal supply means in the SIO with an input from an external circuit, the clock signal supply means which supplies a data transfer clock signal to a serial input-output means.
The initialization means initializes immediately the clock signal supply means at the change in a signal level from an external circuit; thereby, it is possible to decreases the delay of the output start timing of the serial data output from the serial input-output means for the timing of change in the signal level from the external circuit.
A microcomputer according to another aspect of the present invention further comprises a changeover means for changing over an input-output direction of a shift register which constitutes the serial input-output means, a switch having contact points to be connected to the midway in the shift register, and a switch setting means for closing a contact point corresponding to a bit length of a datum.
The switch setting means makes the length of a shift register variable equivalently in changing over contact points to be closed and makes transmission and reception of data having an arbitrary length easy.
A microcomputer of a further aspect according to the present invention is further provided with a comparison means for comparing an input signal and an output signal to and from the shift register.
The comparison means detects immediately the difference between the input signal and the output signal and decreases a detecting load for data collision on a bus in a LAN for example.